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K4X51163PE - L(F)E/G 32Mx16 Mobile DDR SDRAM
1. FEATURES
* VDD/VDDQ = 1.8V/1.8V * Double-data-rate architecture; two data transfers per clock cycle * Bidirectional data strobe(DQS) * Four banks operation * Differential clock inputs(CK and CK) * MRS cycle with address key programs - CAS Latency ( 3 ) - Burst Length ( 2, 4, 8, 16 ) - Burst Type (Sequential & Interleave) * EMRS cycle with address key programs - Partial Array Self Refresh ( Full, 1/2, 1/4 Array ) - Output Driver Strength Control ( Full, 1/2, 1/4, 1/8 ) * Internal Temperature Compensated Self Refresh * All inputs except data & DM are sampled at the positive going edge of the system clock(CK). * Data I/O transactions on both edges of data strobe, DM for masking. * Edge aligned data output, center aligned data input. * No DLL; CK to DQS is not synchronized. * DM0 - DM3 for write masking only. * Auto refresh duty cycle - 7.8us for -25 to 85 C
Mobile DDR SDRAM
2. Operating Frequency
DDR333 Speed @CL21) 83Mhz 166Mhz Speed @CL31)
NOTE: 1) CAS Latency
DDR266 83Mhz 133Mhz
3. Address configuration
Organization 32Mx16
- DM is internally loaded to match DQ and DQS identically.
Bank Address BA0,BA1
Row Address A0 - A12
Column Address A0 - A9
4. Ordering Information
Part No. K4X51163PE-L(F)E/GC6 K4X51163PE-L(F)E/GC3 Max Freq. 166MHz(CL=3),83MHz(CL=2) 133MHz(CL=3),83MHz(CL=2) Interface LVCMOS Package 60FBGA Pb (Pb Free)
- L(F)E : 60FBGA Pb(Pb Free), Normal Power, Extended Temperature(-25 C ~ 85 C) - L(F)G : 60FBGA Pb(Pb Free), Low Power, Extended Temperature(-25 C ~ 85 C) - C6/C3 : 166MHz(CL=3) / 133MHz(CL=3) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.
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5. FUNCTIONAL BLOCK DIAGRAM
Mobile DDR SDRAM
16
LWE LDM
I/O Control
CK, CK
Data Input Register Serial to parallel
Bank Select
32
4Mx32
Output Buffer 2-bit prefetch Sense AMP Refresh Counter Row Buffer Row Decoder
4Mx32 4Mx32 4Mx32
32
16
X16
DQi
Address Register
CK, CK ADD
Column Decoder
LCBR LRAS Col. Buffer
Latency & Burst Length
Strobe Gen.
Data Strobe
LCKE
Programming Register LRAS LCBR LWE LCAS LWCBR
LDM
Timing Register
DM Input Register
CK, CK
CKE
CS
RAS
CAS
WE
DM
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6. Package Dimension and Pin Configuration
< Bottom View*1 >
E1
Mobile DDR SDRAM
< Top View*2 >
60Ball(6x10) FBGA
9 A B C D D1 E
8
7
6
5
4
3
2
1 e A B C D E D F G H J K
1 VSS VDDQ VSSQ VDDQ VSSQ VSS CKE A9 A6 VSS
2 DQ15 DQ13 DQ11 DQ9 UDQS UDM CK A11 A7 A4
3 VSSQ DQ14 DQ12 DQ10 DQ8 N.C. CK A12 A8 A5
7 VDDQ DQ1 DQ3 DQ5 DQ7 N.C. WE CS A10/AP A2
8 DQ0 DQ2 DQ4 DQ6 LDQS LDM CAS BA0 A0 A3
9 VDD VSSQ VDDQ VSSQ VDDQ VDD RAS BA1 A1 VDD
F G H J K E
*2: Top View
Ball Name CK, CK CS CKE A0 ~ A12 A A1 b BA0 ~ BA1 RAS CAS WE L(U)DM L(U)DQS DQ0 ~ 15 VDD/VSS VDDQ/VSSQ
Ball Function System Differential Clock Chip Select Clock Enable Address Bank Select Address Row Address Strobe Column Address Strobe Write Enable Data Input Mask Data Strobe Data Input/Output Power Supply/Ground Data Output Power/Ground
z
*1: Bottom View
< Top View*2 >
#A1 Ball Origin Indicator
K4X51163PE
SEC week XXXX
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[Unit::mm] Symbol A A1 E E1 D D1 e b z Min 0.25 7.9 9.9 0.45 Typ 8.0 6.4 10.0 7.2 0.80 0.50 Max 1.0 8.1 10.1 0.55 0.10
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7. Input/Output Function Description
Symbol CK, CK Type Input Description
Mobile DDR SDRAM
Clock : CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Internal clock signals are derived from CK/CK. Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any banks). CKE is synchronous for all functions except for disabling outputs, which is achieved asynchronously. Input buffers, excluding CK, CK and CKE , are disabled during power-down and self refresh mode which are contrived for low standby power consumption. Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command decoder. All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. Command Inputs : RAS, CAS and WE (along with CS) define the command being entered. Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons to the data on DQ8-DQ15. Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. Address Inputs : Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 determines which mode register( mode register or extended mode register ) is loaded during the MODE REGISTER SET command. Data Input/Output : Data bus Data Strobe : Output with read data, input with write data. Edge-aligned with read data, centered in write data. it is used to fetch write data. For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS corresponds to the data on DQ8-DQ15. No Connect : No internal electrical connection is present. DQ Power Supply : 1.7V to 1.95V DQ Ground. Power Supply : 1.7V to 1.95V Ground.
CKE
Input
CS RAS, CAS, WE
Input Input
LDM,UDM
Input
BA0, BA1
Input
A [n : 0]
Input
DQ LDQS,UDQS NC VDDQ VSSQ VDD VSS
I/O I/O Supply Supply Supply Supply
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8. Functional Description
Figure 1. State diagram
POWER APPLIED POWER ON CKEH DEEP POWER DOWN
Mobile DDR SDRAM
PARTIAL SELF REFRESH
PRECHARGE ALL BANKS
DEEP POWER DOWN
SELF REFRESH
REFS REFSX
EMRS MRS
MRS
IDLE ALL BANKS PRECHARGED
REFA
AUTO REFRESH
CKEL CKEH ACT POWER DOWN
POWER DOWN
CKEH CKEL WRITE WRITEA READA READ READ ROW ACTIVE BURST STOP READ
WRITEA WRITE
WRITEA READA WRITEA PRE PRE PRE
READA
READA
PRE
PRECHARGE PREALL
Automatic Sequence Command Sequence
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9. Mode Register Definition 9.1. Mode Register Set(MRS)
Mobile DDR SDRAM
The mode register is designed to support the various operating modes of Mobile DDR SDRAM. It includes Cas latency, addressing mode, burst length, test mode and vendor specific options to make Mobile DDR SDRAM useful for variety of applications. The default value of the mode register is not defined, therefore the mode register must be written in the power up sequence of Mobile DDR SDRAM. The mode register is written by asserting low on CS, RAS, CAS and WE(The Mobile DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The states of address pins A0 ~ A12 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the mode register. Two clock cycles are required to complete the write operation in the mode register. Even if the power-up sequence is finished and some read or write operation is executed afterward, the mode register contents can be changed with the same command and two clock cycles. This command must be issued only when all banks are in the idle state. If mode register is changed, extended mode register automatically is reset and come into default state. So extended mode register must be set again. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A3, Cas latency(read latency from column address) uses A4 ~ A6, A7 ~ A12 is used for test mode. BA0 and BA1 must be set to low for proper MRS operation.
Figure 2. Mode Register Set
BA1 BA0 A12 ~ A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
0
0
RFU1)
0
0
0
CAS Latency
BT
Burst Length
Mode Register
A3 0 1 A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved
Burst Type Sequential Interleave A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Burst Type Reserved 2 4 8 16 Reserved Reserved Reserved
NOTE : 1) RFU(Reserved for future use) should stay "0" during MRS cycle
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Table 1. Burst address ordering for burst length Burst Length Starting Address (A3, A2, A1, A0) xxx0 xxx1 xx00 4 xx01 xx10 xx11 x000 x001 x010 8 x011 x100 x101 x110 x111 0000 0001 0010 0011 0100 0101 0110 16 0111 1000 1001 1010 1011 1100 1101 1110 1111 Sequential Mode 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3 5, 6, 7,8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6, 7 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6, 7, 8 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,12 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
Mobile DDR SDRAM
Interleave Mode 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11,10,13,12,15,14 2, 3, 0, 1, 6, 7, 4, 5,10,11, 8, 9, 14,15,12,13 3, 2, 1, 0, 7, 6, 5, 4,11,10, 9, 8, 15,14,13,12 4, 5, 6, 7, 0, 1, 2, 3,12,13,14,15, 8, 9, 10,11 5, 4, 7, 6, 1, 0, 3, 2,13,12,15,14, 9, 8,11,10 6, 7, 4, 5, 2, 3, 0, 1,14,15,12,13,10,11, 8, 9 7, 6, 5, 4, 3, 2, 1, 0, 15,14,13,12,11,10, 9, 8 8, 9,10,11,12,13,14,15, 0, 1, 2, 3, 4, 5, 6, 7 9, 8, 11,10,13,12,15,14,1, 0, 3, 2, 5, 4, 7, 6 10,11, 8, 9, 14,15,12,13, 2, 3, 0, 1, 6, 7, 4, 5 11,10, 9, 8, 15,14,13,12, 3, 2, 1, 0, 7, 6, 5, 4 12,13,14,15, 8, 9, 10,11, 4, 5, 6, 7, 0, 1, 2, 3 13,12,15,14, 9, 8,11,10, 5, 4, 7, 6, 1, 0, 3, 2 14,15,12,13,10,11, 8, 9, 6, 7, 4, 5, 2, 3, 0, 1 15,14,13,12,11,10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
2
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9.2. Extended Mode Register Set(EMRS)
Mobile DDR SDRAM
The extended mode register is designed to support partial array self refresh or driver strength control. EMRS cycle is not mandatory and the EMRS command needs to be issued only when either PASR or DS is used. The default state without EMRS command issued is half driver strength, and Full array refreshed. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA1 ,low on BA0(The Mobile DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0 ~ A12 in the same cycle as CS, RAS, CAS and WE going low is written in the extended mode register. Two clock cycles are required to complete the write operation in the extended mode register. Even if the power-up sequence is finished and some read or write operations is executed afterward, the mode register contents can be changed with the same command and two clock cycles. But this command must be issued only when all banks are in the idle state. A0 - A2 are used for partial array self refresh and A5 - A6 are used for driver strength control. "High" on BA1 and"Low" on BA0 are used for EMRS. All the other address pins except A0,A1,A2,A5,A6, BA1, BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes.
Figure 3. Extended Mode Register Set
BA1 BA0 A12 ~ A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
1
0
RFU1)
0
0
0
DS
RFU1)
PASR
Mode Register
DS A6 0 0 1 1 A5 0 1 0 1 Driver Strength Full 1/2 1/4 1/8 A2 0 0 0 0 1 1 1 1
NOTE : 1) RFU(Reserved for future use) should stay "0" during EMRS cycle
PASR A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Refreshed Area Full Array 1/2 Array 1/4 Array Reserved Reserved Reserved Reserved Reserved
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9.3. Internal Temperature Compensated Self Refresh (TCSR)
Mobile DDR SDRAM
1. In order to save power consumption, Mobile DDR SDRAM includes the internal temperature sensor and control units to control the self refresh cycle automatically according to the two temperature ranges ; 45 C and 85 C. 2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored. Self Refresh Current (IDD6) Temperature Range 45 C1) 85 C
NOTE :
-E Full Array 300 600 1/2 Array 270 500 1/4 Array 255 450 Full Array 250 500
-G 1/2 Array 220 400 1/4 Array 205 350 Unit
uA
1) It has +/- 5 C tolerance.
9.4. Partial Array Self Refresh (PASR)
1. In order to save power consumption, Mobile DDR SDRAM includes PASR option. 2. Mobile DDR SDRAM supports three kinds of PASR in self refresh mode; Full array, 1/2 Array, 1/4 Array.
Figure 4. EMRS code and TCSR , PASR
BA1=0 BA0=0 BA1=1 BA0=0
BA1=0 BA0=1 BA1=1 BA0=1
BA1=0 BA0=0 BA1=1 BA0=0
BA1=0 BA0=1 BA1=1 BA0=1
BA1=0 BA0=0 BA1=1 BA0=0
BA1=0 BA0=1 BA1=1 BA0=1
- Full Array
- 1/2 Array
- 1/4 Array Partial Self Refresh Area
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10. Absolute maximum ratings
Parameter Voltage on any pin relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD VDDQ TSTG PD IOS Value -0.5 ~ 2.7 -0.5 ~ 2.7 -0.5 ~ 2.7 -55 ~ +150 1.0 50
Mobile DDR SDRAM
Unit V V V C W mA
NOTE : 1) Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. 2) Functional operation should be restricted to recommend operation condition. 3) Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
11. DC Operating Conditions
Recommended operating conditions(Voltage referenced to VSS=0V, Tc = -25C to 85C) Parameter Supply voltage(for device with a nominal VDD of 1.8V) I/O Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Output leakage current Symbol VDD VDDQ VIH(DC) VIL(DC) VOH(DC) VOL(DC) II IOZ Min 1.7 1.7 0.7 x VDDQ -0.3 0.9 x VDDQ -2 -5 Max 1.95 1.95 VDDQ+0.3 0.3 x VDDQ 0.1 x VDDQ 2 5 Unit V V V V V V uA uA Note 1 1 2 2 IOH = -0.1mA IOL = 0.1mA
NOTE: 1) Under all conditions, VDDQ must be less than or equal to VDD. 2) These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation.
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12. DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, Tc = -25 to 85C) Parameter
Operating Current (One Bank Active)
Mobile DDR SDRAM
Symbol
IDD0
Test Condition
tRC=tRCmin; tCK=tCKmin; CKE is HIGH; CS is HIGH between valid commands; address inputs are SWITCHING; data bus inputs are STABLE all banks idle, CKE is LOW; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE all banks idle, CKE is HIGH; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE all banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE one bank active, CKE is LOW; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE one bank active, CKE is HIGH; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE one bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE one bank active; BL=4; CL=3; tCK = tCKmin; continuous read bursts; I OUT =0 mA address inputs are SWITCHING; 50% data change each burst transfer one bank active; BL = 4; tCK = tCKmin ; continuous write bursts; address inputs are SWITCHING; 50% data change each burst transfer tRC = tRFCmin ; tCK = tCKmin ; burst refresh; CKE is HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE CKE is LOW; t CK = t CKmin ; Extended Mode Register set to all 0's; address and control inputs are STABLE; data bus inputs are STABLE
DDR333 DDR266 Unit Note
70 0.3 mA 0.3 15 8 5 mA 2 25 20 140 115 150 451) 300 270 255 250 220 205 15 25 mA 20 115 mA 100 135 85 600 500 450 500 400 350 uA 2 uA mA C 12 mA 8 65 mA
Precharge Standby Current in power-down mode
IDD2P IDD2PS IDD2N IDD2NS IDD3P IDD3PS IDD3N IDD3NS IDD4R IDD4W
Precharge Standby Current in non power-down mode
Active Standby Current in power-down mode
Active Standby Current in non power-down mode (One Bank Active)
Operating Current (Burst Mode)
Refresh Current
IDD5
Internal TCSR
Full Array
-E
1/2 Array 1/4 Array Full Array
Self Refresh Current
IDD6
-G
Deep Power Down Current IDD8 Deep Power Down Mode Current
1/2 Array 1/4 Array
NOTE : 1) It has +/- 5C tolerance. 2) DPD(Deep Power Down) function is an optional feature, and it will be enabled upon request. Please contact Samsung for more information. 3) IDD specifications are tested after the device is properly intialized. 4) Input slew rate is 1V/ns. 5) Definitions for IDD: LOW is defined as V IN 0.1 * VDDQ ; HIGH is defined as V IN 0.9 * VDDQ ; STABLE is defined as inputs stable at a HIGH or LOW level ; SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once per two clock cycles ; - data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE.
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13. AC Operating Conditions & Timming Specification
Parameter/Condition Input High (Logic 1) Voltage, all inputs Input Low (Logic 0) Voltage, all inputs Input Crossing Point Voltage, CK and CK inputs Symbol VIH(AC) VIL(AC) VIX(AC) Min 0.8 x VDDQ -0.3 0.4 x VDDQ Max
Mobile DDR SDRAM
Unit V V V
Note 1 1 2
VDDQ+0.3 0.2 x VDDQ 0.6 x VDDQ
NOTE : 1) These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. 2) The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
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14. AC Timming Parameters & Specifications
Parameter Clock cycle time Row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Active delay Last data in to Read command Col. address to Col. address delay Clock high level width Clock low level width DQ Output data access time from CK/CK DQS Output data access time from CK/CK Data strobe edge to ouput data edge Read Preamble Read Postamble CK to valid DQS-in DQS-in setup time DQS-in hold time DQS-in high level width DQS-in low level width DQS falling edge to CK setup time DQS falling edge hold time from CK DQS-in cycle time Address and Control Input setup time Address and Control Input hold time Address & Control input pulse width DQ & DM setup time to DQS DQ & DM hold time to DQS DQ & DM input pulse width DQ & DQS low-impedence time from CK/CK DQ & DQS high-impedence time from CK/CK DQS write postamble time DQS write preamble time Refresh interval time Mode register set cycle time Power down exit time CL=2 CL=3 CL=2 CL=3 CL=2 CL=3 CL=2 CL=3 Symbol tCK tRC tRAS tRCD tRP tRRD tWR tDAL tCDLR tCCD tCH tCL tAC tDQSCK tDQSQ tRPRE tRPST tDQSS tWPRES tWPREH tDQSH tDQSL tDSS tDSH tDSC tIS tIH tIPW tDS tDH tDIPW tLZ tHZ tWPST tWPRE tREF tMRD tPDEX 2 1 0.4 0.25 64 2 1 0.5 0.9 0.4 0.75 0 0.25 0.4 0.4 0.2 0.2 0.9 1.1 1.1 2.2 0.6 0.6 1.2 1.0 5.5 0.6 0.4 0.25 1.1 0.6 0.6 DDR333 Min 12.0 6 60 42 18 18 12 12 2tCK+tRP 1 1 0.45 0.45 2 2 2 2 0.55 0.55 8 5.5 8 5.5 0.5 1.1 1.1 0.6 1.25 0.5 0.9 0.4 0.75 0 0.25 0.4 0.4 0.2 0.2 0.9 1.3 1.3 2.6 0.8 0.8 1.8 1.0 70,000 Max Min 12.0 7.5 67.5 45 22.5 22.5 15 15 2tCK+tRP 1 1 0.45 0.45 2 2 2 2
Mobile DDR SDRAM
DDR266 Max
Unit ns ns
Note
70,000
ns ns ns ns ns tCK tCK 2
0.55 0.55 8 6 8 6 0.6 1.1 1.1 0.6 1.25
tCK tCK ns ns ns tCK tCK tCK ns tCK 4 3
0.6 0.6
tCK tCK tCK tCK
1.1
tCK ns ns ns ns ns ns 1 1 1 5,6 5,6
6.0 0.6 64
ns tCK tCK ms tCK tCK
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Mobile DDR SDRAM
Parameter CKE min. pulse width(high and low pulse width) Auto refresh cycle time Exit self refresh to active command Data hold from DQS to earliest DQ edge Data hold skew factor Clock half period NOTE : 1) Input Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate (V/ns) 1.0 0.8 0.6
Symbol tCKE tRFC tXSR tQH tQHS tHP
DDR333 Min 2 72 120 tHPmin tQHS 0.65 tCLmin or tCHmin Max Min 2 80 120
DDR266 Max
Unit tCK ns ns ns
Note
7
tHPmin tQHS 0.75 tCLmin or tCHmin
ns ns
tIS (ps) 0 +50 +100
tIH (ps) 0 +50 +100
This derating table is used to increase tIS/tIH in the case where the input slew rate is below 1.0V/ns. 2) Minimum 3CLK of tDAL(= tWR + tRP) is required because it need minimum 2CLK for tWR and minimum 1CLK for tRP. 3) tAC(min) value is measured at the high Vdd(1.95V) and cold temperature(-25C). tAC(max) value is measured at the low Vdd(1.7V) and hot temperature(85C). tAC is measured in the device with half driver strength and under the AC output load condition (Fig.6 in next Page). 4) The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 5) I/O Setup/Hold Slew Rate Derating I/O Setup/Hold Slew Rate (V/ns) 1.0 0.8 0.6 tIS (ps) 0 +75 +150 tIH (ps) 0 +75 +150
This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 1.0V/ns. 6) I/O Delta Rise/Fall Rate(1/slew-rate) Derating Data Rise/Fall Rate (ns/V) 0 0.25 0.5 tIS (ps) 0 +50 +100 tIH (ps) 0 +50 +100
This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calculated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 1.0V/ns and slew rate 2 =0.8V/ns, then the Delta Rise/Fall Rate =-0.25ns/V. 7) Maximum burst refresh cycle : 8
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K4X51163PE - L(F)E/G
15. AC Operating Test Conditions(VDD = 1.7V to 1.95V, Tc = -25 to 85C)
Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input signal minimum slew rate Output timing measurement reference level Output load condition Value 0.8 x VDDQ / 0.2 x VDDQ 0.5 x VDDQ 1.0 0.5 x VDDQ See Figure 6
Mobile DDR SDRAM
Unit V V V/ns V
1.8V
13.9K Output 10.6K VOH (DC) = 0.9 x VDDQ , IOH = -0.1mA VOL (DC) = 0.1 x VDDQ , IOL = 0.1mA 20pF
Figure 5. DC Output Load Circuit
Vtt=0.5 x VDDQ
50 Output Z0=50 20pF
Figure 6. AC Output Load Circuit
16. Input/Output Capacitance(VDD=1.8, VDDQ=1.8V, TC = 25C, f=1MHz)
Parameter Input capacitance (A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS, WE) Input capacitance( CK, CK ) Data & DQS input/output capacitance Input capacitance(DM) Symbol CIN1 CIN2 COUT CIN3 Min 1.5 1.5 2.0 2.0 Max 3.0 3.5 4.5 4.5 Unit pF pF pF pF
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June 2007
K4X51163PE - L(F)E/G
17. AC Overshoot/Undershoot Specification for Address & Control Pins
Parameter Maximum peak Amplitude allowed for overshoot area Maximum peak Amplitude allowed for undershoot area Maximum overshoot area above VDD Maximum undershoot area below VSS
Mobile DDR SDRAM
Specification 0.9V 0.9V 3V-ns 3V-ns
Maximum Amplitude Overshoot Area
Volts (V)
VDD VSS
Maximum Amplitude Time (ns)
Undershoot Area
Figure 7. AC Overshoot and Undershoot Definition for Address and Control Pins
18. AC Overshoot/Undershoot Specification for CLK, DQ, DQS and DM Pins
Parameter Maximum peak Amplitude allowed for overshoot area Maximum peak Amplitude allowed for undershoot area Maximum overshoot area above VDDQ Maximum undershoot area below VSSQ Specification 0.9V 0.9V 3V-ns 3V-ns
Maximum Amplitude Overshoot Area
Volts (V)
VDDQ VSSQ
Maximum Amplitude Time (ns)
Undershoot Area
Figure 8. AC Overshoot and Undershoot Definition for CLK, DQ, DQS and DM Pins
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June 2007
K4X51163PE - L(F)E/G
19. Command Truth Table
Command Register Mode Register Set Auto Refresh Refresh Entry Self Refresh Exit CKEn-1 H H CKEn X H L H X X CS L L L H L L RAS L L H X L H CAS L L H X H L WE L H H X H H V V
Mobile DDR SDRAM
BA0,1
A10/AP OP CODE X
A12,A11, A9~A0
Note 1, 2 3 3 3 3
L H H
X Row Address L H L H X X V X L H X Column Address (A0~A9) Column Address (A0~A9)
Bank Active & Row Addr. Read & Column Address Write & Column Address Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable Entry Exit
4 4 4 4, 6
H H L H H
X L H X X
L L H L L H L X H L H L
H H X H L X V X X H X V X
L H X H H X V X X H X V
L L X L L X V X X H X V
V
Deep Power Down Burst Stop Precharge
7
Bank Selection All Banks Entry Exit Entry
5
Active Power Down
H L H
L H L
X
Precharge Power Down Exit DM No operation (NOP) : Not defined L H H X H
X
X X H X H X
8 9 9
H L
X H
(V=Valid, X=Don't Care, H=Logic High, L=Logic Low) NOTE : 1) OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2) EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3) Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4) BA0 ~ BA1 : Bank select addresses. 5) If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6) During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7) Burst stop command is valid at every burst length. 8) DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9) This combination is not defined for any function, which means "No Operation(NOP)" in Mobile DDR SDRAM.
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June 2007
K4X51163PE - L(F)E/G
20. Functional Truth Table
Current State CS L L PRECHARGE STANDBY L L L L L L L L L L L L L L L L L L L L RAS H H L L L L H H H L L L L H H H L L L L H H CAS H L H H L L H L L H H L L H L L H H L L H L WE L X H L H L L H L H L H L L H L H L H L L H X BA, CA, A10 X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Address Command Burst Stop READ/WRITE Active PRE/PREA Refresh MRS Burst Stop READ/READA WRITE/WRITEA Active PRE/PREA Refresh MRS Burst Stop READ/READA WRITE/WRITEA Active PRE/PREA Refresh MRS Burst Stop READ/READA
Mobile DDR SDRAM
Action ILLEGAL2) ILLEGAL2) Bank Active, Latch RA ILLEGAL4) AUTO-Refresh5) Mode Register Set5) NOP Begin Read, Latch CA, Determine Auto-Precharge Begin Write, Latch CA, Determine Auto-Precharge Bank Active/ILLEGAL2) Precharge/Precharge All ILLEGAL ILLEGAL Terminate Burst Terminate Burst, Latch CA, Begin New Read, Determine Auto-Precharge3) ILLEGAL Bank Active/ILLEGAL2) Terminate Burst, Precharge10) ILLEGAL ILLEGAL ILLEGAL Terminate Burst With DM=High, Latch CA, Begin Read, Determine Auto-Precharge3) Terminate Burst, Latch CA, Begin new Write, Determine AutoPrecharge3) Bank Active/ILLEGAL2) Terminate Burst With DM=High, Precharge10) ILLEGAL ILLEGAL ILLEGAL 6) ILLEGAL 6) 6) ILLEGAL ILLEGAL
ACTIVE STANDBY
READ
WRITE
L
H
L
L
BA, CA, A10
WRITE/WRITEA
L L L L L READ with AUTO PRECHARGE6) (READA) L L L L L L
L L L L H H H L L L L
H H L L H L L H H L L
H L H L L H L H L H L
BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add
Active PRE/PREA Refresh MRS Burst Stop READ/READA WRITE/WRITEA Active PRE/PREA Refresh MRS
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June 2007
K4X51163PE - L(F)E/G
Mobile DDR SDRAM
Current State
CS L L L L L L L L L
RAS H H H L L L L H H L L L L H H L L L L H H H L L L L H H L L L L H H L L L L
CAS H L L H H L L H L H H L L H L H H L L H L L H H L L H L H H L L H L H H L L
WE L H L H L H L L X H L H L L X H L H L L H L H L H L L X H L H L L X H L H L X
Address BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X
Command Burst Stop READ/READA WRITE/WRITEA Active PRE/PREA Refresh ILLEGAL 7) 7) 7) 7) ILLEGAL ILLEGAL ILLEGAL2) ILLEGAL2) ILLEGAL2)
Action
WRITE with AUTO RECHARGE7) (WRITEA)
Op-Code, Mode-Add MRS X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Burst Stop READ/WRITE Active PRE/PREA Refresh MRS Burst Stop READ/WRITE Active PRE/PREA Refresh MRS Burst Stop READ WRITE Active PRE/PREA Refresh MRS Burst Stop READ/WRITE Active PRE/PREA Refresh MRS Burst Stop READ/WRITE Active PRE/PREA Refresh MRS
PRECHARGING (DURING tRP)
L L L L L
NOP4)(Idle after tRP) ILLEGAL ILLEGAL ILLEGAL2) ILLEGAL2) ILLEGAL2) ILLEGAL2) ILLEGAL ILLEGAL ILLEGAL2) ILLEGAL2) WRITE ILLEGAL2) ILLEGAL2) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
ROW ACTIVATING (FROM ROW ACTIVE TO tRCD)
L L L L L L L
WRITE RECOVERING (DURING tWR OR tCDLR)
L L L L L L L
REFRESHING
L L L L L L L L L L
MODE REGISTER SETTING
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June 2007
K4X51163PE - L(F)E/G
Mobile DDR SDRAM
Current State
CKE n-1 L L
CKE n H H H H H L H L H L H L L L L L L L X
CS H L L L L X X X H X X L H L L L L L X
RAS X H H H L X X X X X X L X H H H H L X
CAS X H H L X X X X X X X L X H H H L X X
WE X H L X X X X X X X X H X H L L X X X
Add X X X X X X X X X X X X X X X X X X X Exit Self-Refresh Exit Self-Refresh ILLEGAL ILLEGAL ILLEGAL
Action
SELFREFRESHING8)
L L L L
NOP (Maintain Self-Refresh) Exit Power Down(Idle after tPDEX) NOP (Maintain Power Down) Exit Deep Power Down10) NOP (Maintain Deep Power Down) Refer to Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down Enter Deep Power Down ILLEGAL ILLEGAL ILLEGAL Refer to Current State=Power Down
(H=High Level, L=Low level, X=Dont Care)
POWER DOWN DEEP POWER DOWN
L L L L H H H H H H H H L
ALL BANKS IDLE9)
NOTE : 1) All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2) ILLEGAL to bank in specified state ; function may be legal in the bank indicated by BA, depending on the state of that bank. (ILLEGAL = Device operation and/or data integrity are not guaranteed.) 3) Must satisfy bus contention, bus turn around and write recovery requirements. 4) NOP to bank precharging or in idle sate. May precharge bank indicated by BA. 5) ILLEGAL if any bank is not idle. 6) Refer to "Read with Auto Precharge Timing Diagram" for detailed information. 7) Refer to "Write with Auto Precharge Timing Diagram" for detailed information. 8) CKE Low to High transition will re-enable CK, CK and other inputs asynchronously. A minimum setup time must be satisfied before issuing any command other than EXIT. 9) Power-Down, Self-Refresh and Deep Power Down Mode can be entered only from All Bank Idle state. 10) The Deep Power Down Mode is exited by asserting CKE high and full initialization is required after exiting Deep Power Down Mode.
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June 2007

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